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Intel SSE MMX2 KNI documentation AMD 64 Bit & Opteron resource on this site Intel Itanium 64 Bit processor Intel 80386 Reference Programmer's Manual Our Partners: |
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Chapter 17 -- 80386 Instruction Set prev: ENTER Make Stack Frame for Procedure Parameters next: IDIV Signed Divide
HLT -- HaltOpcode Instruction Clocks Description F4 HLT 5 Halt OperationEnter Halt state;DescriptionHALT stops instruction execution and places the 80386 in a HALT state. An enabled interrupt, NMI, or a reset will resume execution. If an interrupt (including NMI) is used to resume execution after HLT, the saved CS:IP (or CS:EIP) value points to the instruction following HLT.Flags AffectedNoneProtected Mode ExceptionsHLT is a privileged instruction; #GP(0) if the current privilege level is not 0Real Address Mode ExceptionsNoneVirtual 8086 Mode Exceptions#GP(0); HLT is a privileged instruction
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Chapter 17 -- 80386 Instruction Set |