Intel and compatable CPU's Programming Information
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LAR -- Load Access Rights Byte
Opcode Instruction Clocks Description 0F 02 /r LAR r16,r/m16 pm=15/16 r16 := r/m16 masked by FF00 0F 02 /r LAR r32,r/m32 pm=15/16 r32 := r/m32 masked by 00FxFF00
DescriptionThe LAR instruction stores a marked form of the second doubleword of the descriptor for the source selector if the selector is visible at the CPL (modified by the selector's RPL) and is a valid descriptor type. The destination register is loaded with the high-order doubleword of the descriptor masked by 00FxFF00, and ZF is set to 1. The x indicates that the four bits corresponding to the upper four bits of the limit are undefined in the value loaded by LAR. If the selector is invisible or of the wrong type, ZF is cleared.
If the 32-bit operand size is specified, the entire 32-bit value is loaded into the 32-bit destination register. If the 16-bit operand size is specified, the lower 16-bits of this value are stored in the 16-bit destination register.
All code and data segment descriptors are valid for LAR.
The valid special segment and gate descriptor types for LAR are given in the following table:
Type Name Valid/Invalid 0 Invalid Invalid 1 Available 80286 TSS Valid 2 LDT Valid 3 Busy 80286 TSS Valid 4 80286 call gate Valid 5 80286/80386 task gate Valid 6 80286 trap gate Valid 7 80286 interrupt gate Valid 8 Invalid Invalid 9 Available 80386 TSS Valid A Invalid Invalid B Busy 80386 TSS Valid C 80386 call gate Valid D Invalid Invalid E 80386 trap gate Valid F 80386 interrupt gate Valid
Flags AffectedZF as described above
Protected Mode Exceptions#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
Real Address Mode ExceptionsInterrupt 6; LAR is unrecognized in Real Address Mode
Virtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode