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![]() Intel and compatable CPU's Programming Information ![]() |
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Intel SSE MMX2 KNI documentation AMD 64 Bit & Opteron resource on this site Intel Itanium 64 Bit processor Intel 80386 Reference Programmer's Manual Our Partners: |
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prev: LLDT Load Local Descriptor Table Register next: LOCK Assert LOCK# Signal Prefix
LMSW -- Load Machine Status WordOpcode Instruction Clocks Description 0F 01 /6 LMSW r/m16 10/13 Load r/m16 in machine status word OperationMSW := r/m16; (* 16 bits is stored in the machine status word *) DescriptionLMSW loads the machine status word (part of CR0) from the source operand. This instruction can be used to switch to Protected Mode; if so, it must be followed by an intrasegment jump to flush the instruction queue. LMSW will not switch back to Real Address Mode.LMSW is used only in operating system software. It is not used in application programs. Flags AffectedNoneProtected Mode Exceptions#GP(0) if the current privilege level is not 0; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page faultReal Address Mode ExceptionsInterrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFHVirtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode; #PF(fault-code) for a page faultNotesThe operand-size attribute has no effect on this instruction. This instruction is provided for compatibility with the 80286; 80386 programs should use MOV CR0, ... instead.
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Chapter 17 -- 80386 Instruction Set |