Intel and compatable CPU's Programming Information
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LOCK -- Assert LOCK# Signal Prefix
Opcode Instruction Clocks Description F0 LOCK 0 Assert LOCK# signal for the next instruction
DescriptionThe LOCK prefix causes the LOCK# signal of the 80386 to be asserted during execution of the instruction that follows it. In a multiprocessor environment, this signal can be used to ensure that the 80386 has exclusive use of any shared memory while LOCK# is asserted. The read-modify-write sequence typically used to implement test-and-set on the 80386 is the BTS instruction.
The LOCK prefix functions only with the following instructions:
BT, BTS, BTR, BTC mem, reg/imm XCHG reg, mem XCHG mem, reg ADD, OR, ADC, SBB, AND, SUB, XOR mem, reg/imm NOT, NEG, INC, DEC memAn undefined opcode trap will be generated if a LOCK prefix is used with any instruction not listed above.
XCHG always asserts LOCK# regardless of the presence or absence of the LOCK prefix.
The integrity of the LOCK is not affected by the alignment of the memory field. Memory locking is observed for arbitrarily misaligned fields.
Locked access is not assured if another 80386 processor is executing an instruction concurrently that has one of the following characteristics:
Protected Mode Exceptions#UD if LOCK is used with an instruction not listed in the "Description" section above; other exceptions can be generated by the subsequent (locked) instruction
Real Address Mode ExceptionsInterrupt 6 if LOCK is used with an instruction not listed in the "Description" section above; exceptions can still be generated by the subsequent (locked) instruction
Virtual 8086 Mode Exceptions#UD if LOCK is used with an instruction not listed in the "Description" section above; exceptions can still be generated by the subsequent (locked) instruction