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![]() Intel and compatable CPU's Programming Information ![]() |
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Intel SSE MMX2 KNI documentation AMD 64 Bit & Opteron resource on this site Intel Itanium 64 Bit processor Intel 80386 Reference Programmer's Manual Our Partners: |
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LTR -- Load Task RegisterOpcode Instruction Clocks Description 0F 00 /3 LTR r/m16 pm=23/27 Load EA word into task register DescriptionLTR loads the task register from the source register or memory location specified by the operand. The loaded task state segment is marked busy. A task switch does not occur.LTR is used only in operating system software; it is not used in application programs. Flags AffectedNoneProtected Mode Exceptions#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #GP(0) if the current privilege level is not 0; #GP(selector) if the object named by the source selector is not a TSS or is already busy; #NP(selector) if the TSS is marked "not present"; #PF(fault-code) for a page faultReal Address Mode ExceptionsInterrupt 6; LTR is not recognized in Real Address ModeVirtual 8086 Mode ExceptionsSame exceptions as in Real Address ModeNotesThe operand-size attribute has no effect on this instruction.
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Chapter 17 -- 80386 Instruction Set |