Intel and compatable CPU's Programming Information |
|||
Intel SSE MMX2 KNI documentation AMD 64 Bit & Opteron resource on this site Intel Itanium 64 Bit processor Intel 80386 Reference Programmer's Manual Our Partners: |
prev: NOT One's Complement Negation next: OUT Output to Port
OR -- Logical Inclusive OROpcode Instruction Clocks Description 0C ib OR AL,imm8 2 OR immediate byte to AL 0D iw OR AX,imm16 2 OR immediate word to AX 0D id OR EAX,imm32 2 OR immediate dword to EAX 80 /1 ib OR r/m8,imm8 2/7 OR immediate byte to r/m byte 81 /1 iw OR r/m16,imm16 2/7 OR immediate word to r/m word 81 /1 id OR r/m32,imm32 2/7 OR immediate dword to r/m dword 83 /1 ib OR r/m16,imm8 2/7 OR sign-extended immediate byte with r/m word 83 /1 ib OR r/m32,imm8 2/7 OR sign-extended immediate byte with r/m dword 08 /r OR r/m8,r8 2/6 OR byte register to r/m byte 09 /r OR r/m16,r16 2/6 OR word register to r/m word 09 /r OR r/m32,r32 2/6 OR dword register to r/m dword 0A /r OR r8,r/m8 2/7 OR byte register to r/m byte 0B /r OR r16,r/m16 2/7 OR word register to r/m word 0B /r OR r32,r/m32 2/7 OR dword register to r/m dword OperationDEST := DEST OR SRC; CF := 0; OF := 0 DescriptionOR computes the inclusive OR of its two operands and places the result in the first operand. Each bit of the result is 0 if both corresponding bits of the operands are 0; otherwise, each bit is 1.Flags AffectedOF := 0, CF := 0; SF, ZF, and PF as described in Appendix C; AF is undefinedProtected Mode Exceptions#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page faultReal Address Mode ExceptionsInterrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFHVirtual 8086 Mode ExceptionsSame exceptions as in real-address mode; #PF(fault-code) for a page fault
up:
Chapter 17 -- 80386 Instruction Set |