Intel and compatable CPU's Programming Information |
|||
Intel SSE MMX2 KNI documentation AMD 64 Bit & Opteron resource on this site Intel Itanium 64 Bit processor Intel 80386 Reference Programmer's Manual Our Partners: |
prev: SAHF Store AH into Flags next: SBB Integer Subtraction with Borrow
SAL/SAR/SHL/SHR -- Shift InstructionsOpcode Instruction Clocks Description D0 /4 SAL r/m8,1 3/7 Multiply r/m byte by 2, once D2 /4 SAL r/m8,CL 3/7 Multiply r/m byte by 2, CL times C0 /4 ib SAL r/m8,imm8 3/7 Multiply r/m byte by 2, imm8 times D1 /4 SAL r/m16,1 3/7 Multiply r/m word by 2, once D3 /4 SAL r/m16,CL 3/7 Multiply r/m word by 2, CL times C1 /4 ib SAL r/m16,imm8 3/7 Multiply r/m word by 2, imm8 times D1 /4 SAL r/m32,1 3/7 Multiply r/m dword by 2, once D3 /4 SAL r/m32,CL 3/7 Multiply r/m dword by 2, CL times C1 /4 ib SAL r/m32,imm8 3/7 Multiply r/m dword by 2, imm8 times D0 /7 SAR r/m8,1 3/7 Signed divide^(1) r/m byte by 2, once D2 /7 SAR r/m8,CL 3/7 Signed divide^(1) r/m byte by 2, CL times C0 /7 ib SAR r/m8,imm8 3/7 Signed divide^(1) r/m byte by 2, imm8 times D1 /7 SAR r/m16,1 3/7 Signed divide^(1) r/m word by 2, once D3 /7 SAR r/m16,CL 3/7 Signed divide^(1) r/m word by 2, CL times C1 /7 ib SAR r/m16,imm8 3/7 Signed divide^(1) r/m word by 2, imm8 times D1 /7 SAR r/m32,1 3/7 Signed divide^(1) r/m dword by 2, once D3 /7 SAR r/m32,CL 3/7 Signed divide^(1) r/m dword by 2, CL times C1 /7 ib SAR r/m32,imm8 3/7 Signed divide^(1) r/m dword by 2, imm8 times D0 /4 SHL r/m8,1 3/7 Multiply r/m byte by 2, once D2 /4 SHL r/m8,CL 3/7 Multiply r/m byte by 2, CL times C0 /4 ib SHL r/m8,imm8 3/7 Multiply r/m byte by 2, imm8 times D1 /4 SHL r/m16,1 3/7 Multiply r/m word by 2, once D3 /4 SHL r/m16,CL 3/7 Multiply r/m word by 2, CL times C1 /4 ib SHL r/m16,imm8 3/7 Multiply r/m word by 2, imm8 times D1 /4 SHL r/m32,1 3/7 Multiply r/m dword by 2, once D3 /4 SHL r/m32,CL 3/7 Multiply r/m dword by 2, CL times C1 /4 ib SHL r/m32,imm8 3/7 Multiply r/m dword by 2, imm8 times D0 /5 SHR r/m8,1 3/7 Unsigned divide r/m byte by 2, once D2 /5 SHR r/m8,CL 3/7 Unsigned divide r/m byte by 2, CL times C0 /5 ib SHR r/m8,imm8 3/7 Unsigned divide r/m byte by 2, imm8 times D1 /5 SHR r/m16,1 3/7 Unsigned divide r/m word by 2, once D3 /5 SHR r/m16,CL 3/7 Unsigned divide r/m word by 2, CL times C1 /5 ib SHR r/m16,imm8 3/7 Unsigned divide r/m word by 2, imm8 times D1 /5 SHR r/m32,1 3/7 Unsigned divide r/m dword by 2, once D3 /5 SHR r/m32,CL 3/7 Unsigned divide r/m dword by 2, CL times C1 /5 ib SHR r/m32,imm8 3/7 Unsigned divide r/m dword by 2, imm8 timesNot the same division as IDIV; rounding is toward negative infinity. Operation(* COUNT is the second parameter *) (temp) := COUNT; WHILE (temp <> 0) DO IF instruction is SAL or SHL THEN CF := high-order bit of r/m; FI; IF instruction is SAR or SHR THEN CF := low-order bit of r/m; FI; IF instruction = SAL or SHL THEN r/m := r/m * 2; FI; IF instruction = SAR THEN r/m := r/m /2 (*Signed divide, rounding toward negative infinity*); FI; IF instruction = SHR THEN r/m := r/m / 2; (* Unsigned divide *); FI; temp := temp - 1; OD; (* Determine overflow for the various instructions *) IF COUNT = 1 THEN IF instruction is SAL or SHL THEN OF := high-order bit of r/m <> (CF); FI; IF instruction is SAR THEN OF := 0; FI; IF instruction is SHR THEN OF := high-order bit of operand; FI; ELSE OF := undefined; FI; DescriptionSAL (or its synonym, SHL) shifts the bits of the operand upward. The high-order bit is shifted into the carry flag, and the low-order bit is set to 0.SAR and SHR shift the bits of the operand downward. The low-order bit is shifted into the carry flag. The effect is to divide the operand by 2. SAR performs a signed divide with rounding toward negative infinity (not the same as IDIV); the high-order bit remains the same. SHR performs an unsigned divide; the high-order bit is set to 0. The shift is repeated the number of times indicated by the second operand, which is either an immediate number or the contents of the CL register. To reduce the maximum execution time, the 80386 does not allow shift counts greater than 31. If a shift count greater than 31 is attempted, only the bottom five bits of the shift count are used. (The 8086 uses all eight bits of the shift count.) The overflow flag is set only if the single-shift forms of the instructions are used. For left shifts, OF is set to 0 if the high bit of the answer is the same as the result of the carry flag (i.e., the top two bits of the original operand were the same); OF is set to 1 if they are different. For SAR, OF is set to 0 for all single shifts. For SHR, OF is set to the high-order bit of the original operand. Flags AffectedOF for single shifts; OF is undefined for multiple shifts; CF, ZF, PF, and SF as described in Appendix CProtected Mode Exceptions#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page faultReal Address Mode ExceptionsInterrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFHVirtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode; #PF(fault-code) for a page fault
up:
Chapter 17 -- 80386 Instruction Set |