Intel and compatable CPU's Programming Information
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SHRD -- Double Precision Shift Right
Opcode Instruction Clocks Description 0F AC SHRD r/m16,r16,imm8 3/7 r/m16 gets SHR of r/m16 concatenated with r16 0F AC SHRD r/m32,r32,imm8 3/7 r/m32 gets SHR of r/m32 concatenated with r32 0F AD SHRD r/m16,r16,CL 3/7 r/m16 gets SHR of r/m16 concatenated with r16 0F AD SHRD r/m32,r32,CL 3/7 r/m32 gets SHR of r/m32 concatenated with r32
(* count is an unsigned integer corresponding to the last operand of the instruction, either an immediate byte or the byte in register CL *) ShiftAmt := count MOD 32; inBits := register; (* Allow overlapped operands *) IF ShiftAmt = 0 THEN no operation ELSE IF ShiftAmt >= OperandSize THEN (* Bad parameters *) r/m := UNDEFINED; CF, OF, SF, ZF, AF, PF := UNDEFINED; ELSE (* Perform the shift *) CF := BIT[r/m, ShiftAmt - 1]; (* last bit shifted out on exit *) FOR i := 0 TO OperandSize - 1 - ShiftAmt DO BIT[r/m, i] := BIT[r/m, i - ShiftAmt]; OD; FOR i := OperandSize - ShiftAmt TO OperandSize - 1 DO BIT[r/m,i] := BIT[inBits,i+ShiftAmt - OperandSize]; OD; Set SF, ZF, PF (r/m); (* SF, ZF, PF are set according to the value of the result *) Set SF, ZF, PF (r/m); AF := UNDEFINED; FI; FI;
DescriptionSHRD shifts the first operand provided by the r/m field to the right as many bits as specified by the count operand. The second operand (r16 or r32) provides the bits to shift in from the left (starting with bit 31). The result is stored back into the r/m operand. The register remains unaltered.
The count operand is provided by either an immediate byte or the contents of the CL register. These operands are taken MODULO 32 to provide a number between 0 and 31 by which to shift. Because the bits to shift are provided by the specified register, the operation is useful for multi-precision shifts (64 bits or more). The SF, ZF and PF flags are set according to the value of the result. CS is set to the value of the last bit shifted out. OF and AF are left undefined.
Flags AffectedOF, SF, ZF, PF, and CF as described above; AF and OF are undefined
Protected Mode Exceptions#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
Real Address Mode ExceptionsInterrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
Virtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode; #PF(fault-code) for a page fault