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Intel SSE MMX2 KNI documentation AMD 64 Bit & Opteron resource on this site Intel Itanium 64 Bit processor Intel 80386 Reference Programmer's Manual Our Partners: |
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Chapter 17 -- 80386 Instruction Set prev: SLDT Store Local Descriptor Table Register next: STC Set Carry Flag
SMSW -- Store Machine Status Word
Opcode Instruction Clocks Description
0F 01 /4 SMSW r/m16 2/3,pm=2/2 Store machine status word to EA
word
Operationr/m16 := MSW; DescriptionSMSW stores the machine status word (part of CR0) in the two-byte register or memory location indicated by the effective address operand.Flags AffectedNoneProtected Mode Exceptions#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page faultReal Address Mode ExceptionsInterrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFHVirtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode; #PF(fault-code) for a page faultNotesThis instruction is provided for compatibility with the 80286; 80386 programs should use MOV ..., CR0.
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Chapter 17 -- 80386 Instruction Set |