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![]() Intel and compatable CPU's Programming Information ![]() |
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Intel SSE MMX2 KNI documentation AMD 64 Bit & Opteron resource on this site Intel Itanium 64 Bit processor Intel 80386 Reference Programmer's Manual Our Partners: |
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prev: WAIT Wait until BUSY# Pin is Inactive (HIGH) next: XLAT/XLATB Table Look-up Translation
XCHG -- Exchange Register/Memory with RegisterOpcode Instruction Clocks Description 90 + r XCHG AX,r16 3 Exchange word register with AX 90 + r XCHG r16,AX 3 Exchange word register with AX 90 + r XCHG EAX,r32 3 Exchange dword register with EAX 90 + r XCHG r32,EAX 3 Exchange dword register with EAX 86 /r XCHG r/m8,r8 3 Exchange byte register with EA byte 86 /r XCHG r8,r/m8 3/5 Exchange byte register with EA byte 87 /r XCHG r/m16,r16 3 Exchange word register with EA word 87 /r XCHG r16,r/m16 3/5 Exchange word register with EA word 87 /r XCHG r/m32,r32 3 Exchange dword register with EA dword 87 /r XCHG r32,r/m32 3/5 Exchange dword register with EA dword Operationtemp := DEST DEST := SRC SRC := temp DescriptionXCHG exchanges two operands. The operands can be in either order. If a memory operand is involved, BUS LOCK is asserted for the duration of the exchange, regardless of the presence or absence of the LOCK prefix or of the value of the IOPL.Flags AffectedNoneProtected Mode Exceptions#GP(0) if either operand is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page faultReal Address Mode ExceptionsInterrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFHVirtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode; #PF(fault-code) for a page fault
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Chapter 17 -- 80386 Instruction Set |