Intel and compatable CPU's Programming Information
prev: 7.4 Task Gate Descriptor
next: 7.6 Task Linking
7.5 Task SwitchingThe 80386 switches execution to another task in any of four cases:
An exception or interrupt causes a task switch when it vectors to a task gate in the IDT. If it vectors to an interrupt or trap gate in the IDT, a task switch does not occur . Refer to Chapter 9 for more information on the interrupt mechanism.
Whether invoked as a task or as a procedure of the interrupted task, an interrupt handler always returns control to the interrupted procedure in the interrupted task. If the NT flag is set, however, the handler is an interrupt task, and the IRET switches back to the interrupted task.
A task switching operation involves these steps:
Every task switch sets the TS (task switched) bit in the MSW (machine status word). The TS flag is useful to systems software when a coprocessor (such as a numerics coprocessor) is present. The TS bit signals that the context of the coprocessor may not correspond to the current 80386 task. Chapter 11 discusses the TS bit and coprocessors in more detail .
Exception handlers that field task-switch exceptions in the incoming task (exceptions due to tests 4 thru 16 of Table 7-1) should be cautious about taking any action that might load the selector that caused the exception. Such an action will probably cause another exception, unless the exception handler first examines the selector and fixes any potential problem.
The privilege level at which execution resumes in the incoming task is neither restricted nor affected by the privilege level at which the outgoing task was executing. Because the tasks are isolated by their separate address spaces and TSSs and because privilege rules can be used to prevent improper access to a TSS, no privilege rules are needed to constrain the relation between the CPLs of the tasks. The new task begins executing at the privilege level indicated by the RPL of the CS selector value that is loaded from the TSS.
Table 7-1. Checks Made during a Task Switch NP = Segment-not-present exception GP = General protection fault TS = Invalid TSS SF = Stack fault Validity tests of a selector check that the selector is in the proper table (e.g., the LDT selector refers to the GDT), lies within the bounds of the table, and refers to the proper type of descriptor (e.g., the LDT selector refers to an LDT descriptor). Test Test Description Exception Error Code Selects 1 Incoming TSS descriptor is present NP Incoming TSS 2 Incoming TSS descriptor is marked not-busy GP Incoming TSS marked not-busy 3 Limit of incoming TSS is greater than or equal to 103 TS Incoming TSS -- All register and selector values are loaded -- 4 LDT selector of incoming task is valid TS Incoming TSS 5 LDT of incoming task is present TS Incoming TSS 6 CS selector is valid TS Code segment 7 Code segment is present NP Code segment 8 Code segment DPL matches CS RPL TS Code segment 9 Stack segment is valid GP Stack segment 10 Stack segment is present SF Stack segment 11 Stack segment DPL = CPL SF Stack segment 12 Stack-selector RPL = CPL GP Stack segment 13 DS, ES, FS, GS selectors are valid GP Segment 14 DS, ES, FS, GS segments are readable GP Segment 15 DS, ES, FS, GS segments are present NP Segment 16 DS, ES, FS, GS segment DPL >= CPL (unless these are conforming segments) GP Segment